1. Field of the Invention
The present invention generally concerns improvements to flash Analog-to-Digital Converters (ADCs), such as may be used within delta-sigma (xcex94xcexa3) modulators.
The present invention particularly concerns differential input flash ADCs appropriate for integrated circuit implementation.
2. Description of the Prior Art
2.1 General Background
For mixed-signal ICs with high digital circuit content, single-poly CMOS integrated circuit processes optimized for digital circuits can presently (circa 2000) provide the lowest overall implementation cost. For example, it is preferable to avoid the expense of extra process steps beyond those required for digital circuitryxe2x80x94such as double-poly capacitors, thick-oxide transistors for 5 V operation, or other analog process enhancementsxe2x80x94when analog circuits such as data converters make up only a small portion of the total die area. This is often true even if the lack of analog enhancements significantly increases the area of the analog circuitry.
However, the performance that can be achieved by data converters in a digital-optimized, single-poly CMOS process may limit the extent to which this advantage can be exploited. High-resolution data converters require linear capacitors and low-noise, low-distortion amplifier circuits to implement fundamental building blocks such as sample-and-holds, integrators, and comparators. Though the specific circuits and performance specifications are determined by the data converter""s architecture, the lack of linear capacitors with low parasitic capacitance, and process-related supply voltage restrictions, arising in modern (circa 2000), digital-optimized, single-poly CMOS processes generally present key challenges in realizing high-performance data converters.
In a CMOS process without double-poly capacitors or other thin-oxide, linear capacitor structures, either metal interconnect layers or MOS structures must be used to implement linear capacitors. MOS capacitor structures (MOSCAPs) require special biasing to keep them in an accumulated or depleted operating region and to mitigate their inherent non-linearity. Metal interconnect (metal-metal) capacitors are inherently linear, but for a given value of capacitance, a metal-metal capacitor can require as much as 30 times the area of a double-poly capacitor. Moreover, the bottom plate capacitance of a metal-metal capacitor is comparable to the inter-plate capacitance, while the double-poly capacitor""s parasitic capacitance is typically less than 50% of the inter-plate capacitance.
Process-related limitations on supply voltages to 3.3 V or less restrict signal swings in amplifiers and through analog switches. In switched-capacitor circuits, this necessitates increased sampling capacitances to achieve the target signal to thermal noise ratio. In switched-capacitor integrators, large feedback capacitances may be required to scale the output down to fit within the amplifier""s output swing. Thus, the reduced headroom and increased loading complicate the task of realizing fast settling, low-distortion switched-capacitor circuits.
It might be possible to mitigate these problems through critical refinement of the analog circuits, but a strategy that would use digital processing to minimize the performance requirements of the analog circuits would seemingly make better use of the strengths of a digital-optimized CMOS process.
Multibit xcex94xcexa3 modulation-using mismatch-shaping DACs exemplifies this approach. By reducing the quantization noise power to be shaped out of band relative to two-level quantization, a multibit xcex94xcexa3 can achieve the same SINAD with a lower order xcex94xcexa3 modulator and a lower over-sampling ratio than can a single-bit design. The reduction in xcex94xcexa3 modulator order implies that fewer switched-capacitor stages are required, and the reduced over-sampling ratio relaxes the bandwidth and slew rate requirements on the integrators. The mismatch-shaping DAC in the feedback path causes static DAC mismatch errors to fall predominantly outside the signal band and significantly relaxes the matching requirements on the DAC""s analog components.
See B. H. Leung, S. Sutarja, Multi-bit sigma-delta A/D converter incorporating a novel class of dynamic element matching techniques, IEEE Trans. on Circuits and Systems-II: Analog and Digital Signal Processing, vol. 39, no. 1, pp. 35-51, Jan. 1992; F. Chen, B. H. Leung, A high resolution multibit sigma-delta modulator with individual level averaging, IEEE J. Solid-State Circuits, vol. SC-30, no. 4, pp. 453-460, April 1995; M. J. Story, Digital to analogue converter adapted to select input sources based on a preselected algorithm once per cycle of a sampling-signal, U.S. Pat. No. 5,138,317, Aug. 11, 1992; H. Spence Jackson, Circuit and Method for Canceling Nonlinearity Error Associated with Component Value Mismatches in a Data Converter, U.S. Pat. No. 5,221,926, 11 Oct. 14, 1999 11 Jun. 22, 1993; R. T. Baird, T. S. Fiez, Improved xcex94xcexa3 DAC linearity using data weighted averaging, Proceedings of the IEEE International Symposium on Circuits and Systems, May, 1995; R. T. Baird, T. S. Fiez, Linearity enhancement of multi-bit xcex94xcexa3 A/D and D/A converters using data weighted averaging, IEEE Trans. on Circuits and Systems II: Analog and Digital Signal Processing, vol. 42, no. 12, pp. 753-762, Dec. 1995; R. Schreier, B. Zhang, Noise-shaped multi-bit D/A converter employing unit elements, Electronics Letters, vol. 31, no. 20, pp. 1712-1713, Sept. 28, 1995; R. W. Adams, T. W. Kwan, Data-directed Scrambler for Multi-bit Noise Shaping D/A Converters, U.S. Pat. No. 5,404,142, Apr. 4, 1995; T. W. Kwan, R. W. Adams, R. Libert, A stereo multi-bit S? D/A with asynchronous master-clock interface, IEEE ISSCC Dig. of Tech. Papers, vol. 39, pp. 226-227, Feb. 1996; T. W. Kwan, R. W. Adams, R. Libert, A stereo multibit Sigma Delta DAC with asynchronous master-clock interface, IEEE Journal of Solid-State Circuits, vol. 31, no. 12, pp. 1881-1887, Dec. 1996; I. Galton, Spectral shaping of circuit errors in digital-to-analog converters, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 44, no. 10, pp. 808-817, Oct. 1997; and I. Galton, Spectral Shaping of Circuit Errors in Digital-to-Analog Converters, U.S. Pat. No. 5,684,482, Nov. 4, 1997.
The multibit approach eases the design requirements on the switched-capacitor circuits, but it also introduces several new design challenges. The transfer function from the first integrator input to the xcex94xcexa3 modulator output provides no noise shaping. Therefore, the first stage feedback DAC must have the same signal-band precision as the overall data converter. Furthermore, the reduced xcex94xcexa3 modulator order and over-sampling ratio imply that the noise transfer function provides less attenuation of circuit noise and distortion in the flash ADC quantizer relative to single-bit designs. Thus the flash ADC must provide sufficient common mode noise rejection and SFDR performance to meet the overall data converter""s performance targets.
The present invention contemplates improvements to conventional so-called flash analog-to-digital converters (ADCs). Flash ADCS are used in a variety of applications, one example of which is as internal components within so-called delta-sigma (xcex94xcexa3) modulator circuits for performing very precise analog-to-digital conversion.
The first improvement contemplated is to realize a differential-input flash ADC using digital common-mode rejection wherein the output sequences from two non-differential flash ADCs are (i) differenced, and (ii) further processed, in the digital domain.
The second improvement contemplated, which is realizable separately and independently of the first improvement, is to effect comparator offset dynamic element matching as a means of reducing the deleterious effects of ADC error resulting from the inevitable non-zero offset voltages of the comparators from which a flash ADC is constructed.
Both improvements are directed at improving the analog-to-digital conversion performance of flash ADCs, especially when used as sub-components within larger circuitsxe2x80x94such as a delta-sigma (xcex94xcexa3) modulator ADCsxe2x80x94that are implemented in a technology optimized for digital circuits, particularly including single-poly CMOS technology.
In integrated circuits, differential signals are often used where information is represented as the difference between two voltages. To perform analog-to-digital (A/D) conversion on such signals, an analog-to-digital converter (ADC) is required to perform A/D conversion of the difference between its two input terminals. The existing methods of implementing such an ADC, referred to as a xe2x80x9cdifferential ADCxe2x80x9d, are problematic for various reasons when integrated circuit technology optimized for digital circuits is employed.
In accordance with the present invention, these problems are circumvented by (1) use of a pair of non-differential ADCs to A/D convert the two input voltages separately, followed by (2) a digital differencing operation followed by (3) a re-quantization function. The (2) differencing operation generates the desired difference signal, but has the drawback that the signal has twice as many quantization levels as would normally be required to represent the information. The (3) re-quantization reduces the number of levels by two in such a way that the information content of the signal is not significantly corrupted.
Alternatively, in a variant of the invention, the non-differential ADCs (1) convert the two input voltages into quantized signals of approximately half the desired number of quantization levels, and when these signals are subsequently subjected to (2) a digital differencing operation then the desired number of quantization levels is restored. In this variant, a requantization function (3) is not required.
Flash ADCs are implemented with voltage comparators that compare the input voltage to a set of nominally evenly spaced reference voltages. Ideally, a voltage comparator generates a digital xe2x80x9chighxe2x80x9d output voltage when the voltage difference between its two input terminals is greater than zero, and a digital xe2x80x9clowxe2x80x9d output voltage if the difference is less than zero. Thus, the xe2x80x9ccomparison thresholdxe2x80x9d between voltages is ideally zero. Unfortunately, mismatches in the fabrication process cause real-world voltage comparators have comparison thresholds that differ from zero by a so-called xe2x80x9coffset voltagexe2x80x9d, and this phenomenon can cause significant error in flash ADCs.
The second improvement in accordance with the present invention deals with this problem by pseudo-randomly modulating the comparison threshold in a positive and negative sense such that the error from the offset voltages as seen at the output of the flash ADC is scrambled.
This pseudo-random offset modulation is realized by (i) dynamically interchanging or not interchanging the two input voltages applied to each comparator, and simultaneously (ii) inverting or not inverting the comparator output, depending upon whether a pseudo-random bit sequence, generated, for example, by a linear feedback shift register pseudo-random sequence generator, is either high or low. The comparator input voltage interchanging operation is implemented via analog switches such as transmission gates, and the comparator output inversion operation can be implemented using digital logic gates or, if differential comparator outputs are available, via analog or digital switches such as transmission gates.
The same pseudo-random bit sequence may be used to control all of the above-mentioned interchanging and inverting operations within the flash ADC. Because the interchanging of the two input signals to each comparator is matched by the inversion of the comparator output signal, the polarity of the comparator output signal is unaffected, except when the two comparator input signals differ by less than the offset voltage of the comparator. In this fashion, the effective polarity of the offset voltages of the all the comparators in the flash ADC are modulated in a pseudo-random fashion with the benefit that a significant portion of the harmonic distortion that would otherwise be introduced by the presence of fixed offset voltages is instead converted to white noise.
This second improvement of the present inventionxe2x80x94an improvement to the use of comparators within ADCsxe2x80x94is independent of the first improvement of the present inventionxe2x80x94an improvement to the design of differential-input flash ADCs. However, both improvements are related in that they are beneficial to the design of flash ADCs in integrated circuit processes that are optimized for digital circuitry. Since increasing integration of analog and digital functionality within a single integrated circuit is desired for applications such as wireless telephony, the improvements of the present invention constitute steps toward implementing, and using, ADCs with high precision in a digital technology environment.
These and other aspects and attributes of the present invention will become increasingly clear upon reference to the following drawings and accompanying specification.